1. Field of the Invention
The present invention relates generally to a configurable system on a chip (CSoC), and specifically to structures and methods regarding the configuration of the CSoC.
2. Description of the Related Art
Programmable logic devices, such as field programmable logic devices (FPLDs), are programmed to perform user-specified logic functions by loading configuration data into the FPLD. This configuration data is typically loaded into the FPLD as a bitstream, i.e. a string of binary bits. Each bit programs a specific programmable resource on the device. Thus, some bits configure the logic blocks which perform the user-defined logic functions, other bits configure the input/output blocks which interface to devices external to the FPGA, and yet other bits configure the programmable interconnect that connects the logic blocks and the input/output blocks.
Typically, the configuration data is stored in a nonvolatile memory device and loaded into the FPLD upon device power-up. The configuration information is loaded into the FPLD in data frames using a shift register. This shift register has N serially coupled one-bit shift registers, each register clocked by the same clock signal. As the bitstream is serially shifted into the shift register, the bits of the shift register are bit shifted downstream in a synchronized manner.
Once the shift register is fully loaded, thereby indicating a frame of data is complete, the stored N bits are transferred simultaneously via dedicated lines to some of the configuration memory cells. Typically, the configuration memory cells are in an array, wherein a frame of data corresponds to one column of configuration memory cells in that array. After the write cycle is complete, the loading of another frame of configuration data begins. These store and write cycles continue until all of the bits of the configuration bitstream are written into the FPLD.
Certain programming limitations are inherent in such FPLDs. For example, because each bit corresponds to a specific programmable resource and each frame of configuration data is loaded in a fixed sequence, reconfiguration of many FPLDs is an “all or nothing” process. In other words, because there is no way to restrict reconfiguration to a part of the device, the entire bitstream must be reloaded into the FPLD. Moreover, the shift register and dedicated lines take up valuable silicon real estate.
Therefore, a need arises for a structure and method of providing programmable logic solutions, while at the same time ensuring more efficient use of silicon and system resources.